Design method for integrated circuit having scan function

Abstract

The present invention provides a method for designing LSI including a logic circuit equipped with a scan circuit without generating a hard-macro library for the scan flip flops constituting the scan circuit. According to the method, first netlist NLis converted into second netlist NLby adding scan circuit including scan flip-flops. Order data for connecting scan chain of the scan circuit is extracted from the second netlist NL. Such second netlist NLis converted into third netlist NLincluding only hard-macros, and the third netlist NLis laid-out by re-ordering the scan chain so that the newly generated order data for is stored temporally. Fourth netlist NLincluding scan circuit formed by scan flip-flops of soft-macros is generated on the basis of the stored order data, then the fourth netlist NLis converted into fifth netlist NLby substituting the scan flip-flops of soft-macros for standard cells of hard-macros. Finally the generated fifth netlist is laid-out without re-ordering the scan chain.