The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 24, 2006

Filed:

Jun. 12, 2002
Applicants:

Eiji Fujiwara, Shinjuku-ku, Tokyo 169-0051, JP;

Jiro Kinoshita, Yamanashi, JP;

Inventors:

Eiji Fujiwara, Shinjuku-ku, Tokyo 169-0051, JP;

Jiro Kinoshita, Yamanashi, JP;

Assignees:

Fanuc LTD, Yamanashi, JP;

Other;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03M 13/03 (2006.01);
U.S. Cl.
CPC ...
Abstract

A syndrome S is found from a received information D and a parity check matrix for correcting burst errors up to b bits. The syndrome S is inputted to p sets of burst error pattern generation circuits that correspond to information frames overlapping each other by (b−1) bits and each having a length of 2b bits. If a burst error is included entirely in any one of the p sets of burst error pattern generation circuits, then the burst error pattern is outputted. An error pattern calculation circuit executes OR respectively on overlapping bits output from the error pattern generation circuits. By executing exclusive OR on an output of the error pattern calculation circuit and received information D, corrected information Dis obtained. As a result, a burst error in the received information can be detected and corrected.


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