Device and method for multi-ported, single bus-mastering data buffer management

Abstract

An architecture, method, and apparatus for managing a data buffer (Data Buffer Management DBM). A data buffer within the DBM is an unified linear memory space, and is divided into numbered physical pages with a predetermined page size. A memory map translates logical address spaces for storing/reading DBM transferred data to the physical address spaces. Each packet to be written into DBM is assigned a frame number or frame handler; thereafter, that frame number will be passed by the original owner (a device attached to the data buffer) to different processes for reading out and/or modifying the associated packet or packet data. Frame number assignment is done prior to actual data transfer by request of the data owner. The frame number request is done prior to moving data from the owner's local memory into the DBM's data buffer. Frame number is allocated dynamically by the DBM. Frame number requests, transfer of frame numbers and other admin functions of the transfer are carried out over an M bus and the DMA transfer of data is performed on an F bus, each of which are coupled to the DBM and the attached devices.