The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 24, 2006
Filed:
Jan. 22, 2002
David Michael Friend, Rochester, MN (US);
David Arnold Luick, Rochester, MN (US);
Nghia Van Phan, Rochester, MN (US);
David Michael Friend, Rochester, MN (US);
David Arnold Luick, Rochester, MN (US);
Nghia Van Phan, Rochester, MN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Apparatus and method for performing fast arithmetic operations, including addition, in a pipelined circuit. In one embodiment, the apparatus comprises a plurality of gates, the critical path through the plurality of gates being three gates delays for some embodiments. The apparatus may comprise: a first level of logic for receiving at least two binary numbers and generating multi-bit P, G, Z, and K carry signals; a second level of logic receiving the multi-bit P, G, Z, and K carry signals and generating multi-bit section-based carry signals; and a third level of logic receiving the multi-bit section-based carry signals and generating a sum of the received binary numbers, the third level of logic comprising: a plurality of domino logic gates forming sum bits using the multi-bit section-based P, G, Z, and K carry signals.