The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 24, 2006
Filed:
Sep. 11, 2001
Haneef D. Mohammed, Beaverton, OR (US);
Rochan Sankar, San Jose, CA (US);
Haneef D. Mohammed, Beaverton, OR (US);
Rochan Sankar, San Jose, CA (US);
Cypress Semiconductor Corp., San Jose, CA (US);
Abstract
A programmable logic block in an integrated circuit comprising a plurality of macrocells, an AND-array, an OR-array, and a logic circuit. The plurality of macrocells may comprise logic that may be configured to (i) generate and propagate an inverted carry-input signal and (ii) generate a sum bit. The AND-array may comprise at least two product terms per macrocell. The OR-array may be configured to generate a sum-of-products term for each macrocell in response to the two product terms. The logic circuit may be configured to (a) receive (i) the product terms and (ii) the carry-input signal generated by a first macrocell of the plurality of macrocells and (b) generate (i) a block carry-propagate signal, (ii) a block carry-generate signal, and (iii) a block carry-output signal.