The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 24, 2006

Filed:

Jul. 23, 2001
Applicants:

Masanori Nakatsuji, Ibaraki, JP;

Masanobu Tanaka, Hirakata, JP;

Hideyo Uwabata, Takatsuki, JP;

Naoji Okumura, Mino, JP;

Kazunori Yamate, Ibaraki, JP;

Inventors:

Masanori Nakatsuji, Ibaraki, JP;

Masanobu Tanaka, Hirakata, JP;

Hideyo Uwabata, Takatsuki, JP;

Naoji Okumura, Mino, JP;

Kazunori Yamate, Ibaraki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 3/23 (2006.01);
U.S. Cl.
CPC ...
Abstract

A write PLL circuit generates a write clock signal for writing a video signal into a line memory. A readout PLL circuit generates a read clock signal for reading out the video signal stored in the line memory. An inner pincushion distortion correction voltage generation circuit modulates a correction waveform in the horizontal scanning period of time by a correction waveform in the vertical scanning period of time, to generate an inner pincushion distortion correction waveform, and adds a DC correction pulse to the inner pincushion distortion correction waveform and outputs the inner pincushion distortion correction waveform as an inner pincushion distortion correction voltage. A capacitive coupling circuit superimposes the inner pincushion distortion correction voltage on an output voltage of a loop filter of the readout PLL circuit, and feeds the inner pincushion distortion correction voltage to a VCO as a control voltage.


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