The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 24, 2006
Filed:
Jun. 15, 2004
Tetse Jang, San Jose, CA (US);
Scott Te-sheng Lien, Palo Alto, CA (US);
Tetse Jang, San Jose, CA (US);
Scott Te-Sheng Lien, Palo Alto, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
Methods of implementing routing matrices for programmable logic devices (PLDs). Each method includes generating a seed matrix, a distribution matrix, adjustment values for the distribution matrix, and a routing matrix pattern. The seed matrix and distribution matrix are implemented according to a set of rules that define valid matrices. The routing matrix is then implemented by applying the routing matrix pattern to provide programmable interconnections between input and output terminals of the routing matrix. Each signal value in the routing matrix pattern corresponds to one of the input terminals, and each row of signal values in the routing matrix pattern corresponds to a set of the input terminals programmably coupled to a different one of the output terminals. By adding additional columns of sub-matrices to an existing distribution matrix, an existing routing matrix can also be expanded to accommodate a larger number of input signals.