The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6988230 B1

PDF
Full Text
Expired
Date of Patent:
Jan. 17, 2006

Filed:

Sep. 17, 2002
Applicants:

Hubertus Gerardus Hendrikus Vermeulen, Eindhoven, NL;

Thomas Franciscus Waayers, Eindhoven, NL;

Guillaume Elisabeth Andreas Lousberg, Eindhoven, NL;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

An electronic device has a plurality of subdevices with each subdevice coupled to a test interface. The test interfaces are arranged in a chain of test interfaces by coupling the TDO contact of a predecessor test interface to the TDI contact of a successor test interface in the chain. In addition, at its beginning, the chain is extended with a boundary scan compliant test interface for testing other parts of electronic device. Both the TDO contact of the last test interface in the chain as well as the TDO contact of test interface are coupled to a bypass multiplexer, thus yielding two possible routes from test data input to test data output: through the full chain or through test interface only. Consequently, electronic device can be tested or debugged as a macro device or as a collection of subdevices.


Find Patent Forward Citations

Vermeulen, Hubertus Gerardus Hendrikus. (2006). Test arrangement for assemblages of intergrated circuit blocks (U.S. Patent No. 6988230). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6988230

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