Synchronous semiconductor memory device with input-data controller advantageous to low power and high frequency

Abstract

There is provided a synchronous memory device having a simplified data input unit for receiving and transferring data to an internal memory cell block, which is adapted to high frequency and can reduce a power consumption. The synchronous memory device includes: a data alignment unit for aligning in parallel a plurality of data sequentially inputted through one data input pin as many as the number of prefetched data to generate a plurality of aligned data; a global I/O line driving unit for receiving the plurality of aligned data and outputting the even data or the odd data to a memory core area in response to a data input strobe signal; a data input strobe signal generating unit for buffering the clock signal to output the data input strobe signal; and a data input strobe signal control unit for generating a data input strobe control signal used to allow the data input strobe signal generating unit to output the data input strobe signal only at a period when an operation corresponding to the write command is carried out.