The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 17, 2006
Filed:
Apr. 02, 2004
Ivan E. Sutherland, Santa Monica, CA (US);
Robert J. Bosnyak, Tacoma, WA (US);
Robert J. Drost, Mountain View, CA (US);
Ivan E. Sutherland, Santa Monica, CA (US);
Robert J. Bosnyak, Tacoma, WA (US);
Robert J. Drost, Mountain View, CA (US);
Sun Microsystems, Inc, Santa Clara, CA (US);
Abstract
A system is presented for latching and amplifying a capacitively coupled inter-chip communication signal that operates by receiving an input signal on a capacitive receiver pad and feeding the input signal through an inverter to produce an output signal. The output signal is fed back through a weakened inverter to produce a feedback signal that is fed into an input of the inverter to form a latch for the input signal. The weakened inverter is biased to produce a feedback signal that swings between a high bias voltage, V, and a low bias voltage, V. Vis set slightly higher than the switching threshold of the inverter, and Vis set slightly lower than the switching threshold. This feedback signal causes the input signal to reside within a narrow voltage range near the switching threshold of the inverter, thereby making the inverter sensitive to small transitions in the input signal.