System and method for a family of digital subscriber line (xdsl) signal processing circuit operating with an internal clock rate that is higher than all communications ports operating with a plurality of port sampling clock rates

Abstract

A communications system operates with an internal pipeline clock rate that is higher than that of any port used in the system. In an xDSL environment, this rate is higher than a DMT symbol rate used in the channel. In this manner, communications for the various ports can be synchronized and pipelined for transmit/receive operations. In addition, the higher rate results in idle processing periods, during which stuffing symbols are generate to maintain synchronism and/or pass along control information. The internal pipeline clock rate is selected to be higher than rate that may be encountered as well during an initialization routine and normal transmissions. The pipeline clock is also programmable so as to permit power management of the system.