The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 10, 2006
Filed:
Aug. 17, 2004
Paul T. Sasaki, Sunnyvale, CA (US);
Jason R. Bergendahl, Sunnyvale, CA (US);
Atul Ghia, San Jose, CA (US);
Jian Tan, Fremont, CA (US);
Paul T. Sasaki, Sunnyvale, CA (US);
Jason R. Bergendahl, Sunnyvale, CA (US);
Atul Ghia, San Jose, CA (US);
Jian Tan, Fremont, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
Method and apparatus for a bimodal serial to parallel converter is provided. A first stage of registers is clocked responsive to a clock signal, such as a forwarded clock signal of a synchronous interface. The first stage of registers is configurable in either a single serial shift chain or two serial shift chains. The former configuration is for Single Data Rate ('SDR') data, and the latter configuration is for Double Data Rate ('DDR') data. A bitslip controller is configured to provide a control select signal to selection circuitry. For DDR operation, the control signal is for selecting respective portions of outputs from the two serial shift chains for providing to a second stage of registers. For DDR operation, the second stage of registers is alternatively clocked responsive to a divided down version of the clock signal and another divided down version of the clock signal which is periodically stopped.