The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 10, 2006
Filed:
May. 11, 2004
Paul W. Bond, Hurley, NY (US);
Daniel F. Casper, Poughkeepsie, NY (US);
Edward Chencinski, Poughkeepsie, NY (US);
Joseph M. Hoke, Millerton, NY (US);
Robert R. Livolsi, Shokan, NY (US);
Paul W. Bond, Hurley, NY (US);
Daniel F. Casper, Poughkeepsie, NY (US);
Edward Chencinski, Poughkeepsie, NY (US);
Joseph M. Hoke, Millerton, NY (US);
Robert R. Livolsi, Shokan, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Initialization of a bidirectional, self-timed parallel interface with capacitive coupling is provided. The self-timed interface includes master and slave nodes connected by a parallel bus comprising multiple AC differential wire pairs. The initialization includes automatically testing at least one wire pair of the multiple AC differential wire pairs for conductivity failure, wherein the testing is responsive to a link reset signal of a first frequency. The automatically testing includes employing a link test signal of a second frequency to test the at least one wire pair of the multiple AC differential wire pairs. The second frequency is a lower frequency than a third, operational signal frequency of the self-timed parallel interface, and the first frequency and the second frequency comprise different frequencies. An initialization testing and handshake approach between the master node and slave node is also provided.