The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 10, 2006
Filed:
Apr. 11, 2002
Wolfgang Gustin, Dresden, DE;
Kae-horng Wang, Dresden, DE;
Matthias Kroenke, Dresden, DE;
Infineon Technologies AG, Munich, DE;
Abstract
The invention relates to a method for the production of an integrated circuit, comprising the following steps: a substrate () is provided with at least one first, second and third gate stack (GS, GS, GS) of approximately the same height surface of said substrate, a common active area () being provided on the surface of the substrate in said substrate () between the first and second gate stack (GS, GS); a first insulating layer () is provided in order to cover the embedding of the first second and third gate stack (GS, GS, GS); the upper side of a gate connection () of the third gate stack (GS) is uncovered; a second insulating layer () is provided in order to cover the upper side of a gate connection (); a mask (M) is provided on the resulting structure having a first opening () above the uncovered upper side of the gate connection () of the third gate stack (GS), a second opening (F) above the substrate () between the third and second gate stack (GS, GS) and a third opening (F) above the common active area (), partially overlapping the first and second gate stack (GS, GS), and simultaneously forming a first, second and third contact hole (KB, KS, KG) using said mask () in an etching process, the first contact hole (KB) uncovering the common active area () on the surface of the substrate between the first and second gate stack (GS, GS), the second contact hole (KS) uncovering the surface of the substrate between the second and third gate stack (GS, GS) and the third contact hole (KG) uncovering the upper side of the gate connection () of the third gate stack (GS).