The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2006

Filed:

Jan. 17, 2004
Applicants:

Kirby H. Spalding, San Jose, CA (US);

Stanley M. Chang, Cupertino, CA (US);

Robert M. Fujioka, Cupertino, CA (US);

Patrick M. Weiher, Los Altos, CA (US);

Inventors:

Kirby H. Spalding, San Jose, CA (US);

Stanley M. Chang, Cupertino, CA (US);

Robert M. Fujioka, Cupertino, CA (US);

Patrick M. Weiher, Los Altos, CA (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01R 12/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An electrical connector semiconductor package with electrically conductive 'fly-over' paths wherein semiconductor package hermetically seals one or more substrate comprising one or more semiconductor devices, such as active or passive ICs, and other semiconductor components. Semiconductor package with 'fly-over' paths comprises a first package face comprising a first set of connector terminations, such as a set of connector pins that receive a set of incoming external signal. Semiconductor package with “fly-over” paths also comprises a second package face comprising a second set of connector termination, wherein the second set of connector terminations might comprise a set of connector pin cusps to couple to an external board or another connector. One or more of the first set of connector terminations are provided to couple a set of incoming external signals to the one or more semiconductor devices on a substrate via a set of signal pins.


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