The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 03, 2006
Filed:
Jan. 24, 2003
Shawn K. Morrison, San Jose, CA (US);
Andrew K. Percey, Sunnyvale, CA (US);
John D. Logue, Placerville, CA (US);
James M. Simkins, Park City, UT (US);
Nicholas J. Sawyer, Opio, FR;
Shawn K. Morrison, San Jose, CA (US);
Andrew K. Percey, Sunnyvale, CA (US);
John D. Logue, Placerville, CA (US);
James M. Simkins, Park City, UT (US);
Nicholas J. Sawyer, Opio, FR;
Xilinx, Inc., San Jose, CA (US);
Abstract
Method and apparatus for providing a measure of jitter and skew of a clock signal is described. The clock signal may be used as an input to a digital circuit. In one embodiment, a digital delay circuit is used in conjunction with a processing circuit to continuously measure the jitter of an input clock signal, thus providing clock signal performance measurement over time. In another embodiment, a pair of digital delay circuits are used to continuously measure the skew or delay between a reference clock signal and a input clock signal, thus providing a measurement of the skew of the input clock signal over time. The digital delay circuit(s) are formed on-chip, and thus an on-chip determination of jitter or skew may be provided.