The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 03, 2006
Filed:
Mar. 27, 2003
Martin L. Voogel, Los Altos, CA (US);
Austin H. Lesea, Los Gatos, CA (US);
Joseph J. Fabula, Tuscon, AZ (US);
Carl H. Carmichael, Campbell, CA (US);
Shahin Toutounchi, Pleasanton, CA (US);
Michael J. Hart, Palo Alto, CA (US);
Steven P. Young, Boulder, CO (US);
Kevin T. Look, Fremont, CA (US);
Jan L. DE Jong, Cupertino, CA (US);
Martin L. Voogel, Los Altos, CA (US);
Austin H. Lesea, Los Gatos, CA (US);
Joseph J. Fabula, Tuscon, AZ (US);
Carl H. Carmichael, Campbell, CA (US);
Shahin Toutounchi, Pleasanton, CA (US);
Michael J. Hart, Palo Alto, CA (US);
Steven P. Young, Boulder, CO (US);
Kevin T. Look, Fremont, CA (US);
Jan L. de Jong, Cupertino, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
SEU-hardening series resistances loads are formed within the gate structures of cross-coupled inverters of a latch. For some embodiments, the gate contact for the input of each cross-coupled inverter has a sufficiently high resistance to provide the SEU-hardening series resistance. For other embodiments, a conductive trace layer coupled to the input of each cross-coupled inverter includes a high-resistivity portion that provides the SEU-hardening series resistance.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile