The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2006

Filed:

Apr. 15, 2003
Applicants:

Ju-wan Kim, Seoul, KR;

Shin-hye Kim, Yongin-si, KR;

Ju-bum Lee, Yongin-si, KR;

Hyong-soo Kim, Suwon-si, KR;

Inventors:

Ju-Wan Kim, Seoul, KR;

Shin-Hye Kim, Yongin-si, KR;

Ju-Bum Lee, Yongin-si, KR;

Hyong-Soo Kim, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01); H01L 21/31 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacturing a semiconductor device by which a generation of a void is prevented after depositing an interlayer dielectric material. First, a plurality of conductive patterns are formed on a substrate and then, a capping insulation layer is formed on the conductive patterns. The capping insulation layer is treated with plasma, and an interlayer dielectric material is deposited on the plasma treated capping insulation layer. The dependency of the interlayer dielectric on the type of material and form of an underlying layer is reduced to improve a gap-filling characteristic, especially for a gap having a high aspect ratio. An improved gap-filling characteristic is accomplished and the formation of all or substantially all of the voids from forming in a gap is prevented even though an interlayer dielectric is deposited under a conventional deposition conditions.


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