The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 03, 2006
Filed:
Aug. 24, 2004
Chiaki Kudo, Amagasaki, JP;
Chiaki Kudo, Amagasaki, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
In an interconnection mask pattern generation, there are suppressed a decrease in reliability of an interconnection and a decrease in manufacture yield, which are resulted from use of an interconnection pattern generated with single minimum line width data for a semiconductor device or the like. When a layout interconnection pattern on a mask for an interconnection which connects functional elements to each other being arranged based on logical circuit data is generated, an interconnection pattern based on the minimum line width data is generated, an interconnection pattern based on the minimum line spacing data is also generated, and an interconnection pattern arranging a new interconnection boundary in the middle of both of them is then generated to be used as a final interconnection pattern, so that the interconnection pattern width becomes properly thick in width, thereby making it possible to improve reliability of the interconnection and suppress a decrease in manufacturing yield.