The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 27, 2005
Filed:
Nov. 27, 2002
Hsing-fa Wang, Taichung, TW;
Ming-chuan Lin, Taichung, TW;
Hsing-Fa Wang, Taichung, TW;
Ming-Chuan Lin, Taichung, TW;
Wintek Corporation, Taichung, TW;
Abstract
The present invention provides a method of ITO layout to make IC bear the high-volt electro static discharge, wherein the major steps include: designing the suitable circuit impedance and Layout at the position of Driver IC bonding and Interface on LCD Module(COG type) in accordance with the function and use of each pin; improving the protection function of ESD(Electro Static Discharge) in increasing the LCD Module assembly on the product of the client; wherein: connecting the pins of all VDD or VSS together at the bottom of the IC and the width of ITO layout spreading over the bottom of IC without influencing the layout of other pins after connecting VSS or VDD. Discharge the static electricity that enters the position of Module Interface and dissipate the electro static discharge by means of the ITO layout design of the big area to improve the protection ability of IC for the electro static discharge. Serial connect an extremely high impedance(3K˜50K Ω) in the Reset Pin. Increase the value (100˜1000 Ω) of ITO circuit impedance of Date bus, such as CS1.D/C,WR,RD,D0˜D7,C86 etc.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile