Programmable controller with sub-phase clocking scheme

Abstract

A parallel processor with a built-in sub-phase clocking scheme is provided to execute sequentially executed programmable logic controller (PLC) programs in a parallel method. A translator program will translate the PLC logic design from a coding language into Electronic Design Interchange Format and that will be eventually converted to a hardware or software embodiment of the logic. The processor provides a plurality of sub-phase clock periods. The translator assigns to the same sub-phase period program elements that process their tasks in the same range of time. The elements are grouped into sub-phase so that logic elements are performed lock-step to ensure that downstream element are performed at a time when they have valid values at their inputs. The processor consequently avoids race conditions in the system and allows the parallel execution speedup of programs written for a sequential machine such as a PLC.