The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 27, 2005
Filed:
Apr. 24, 2003
Eric J. Fluhr, Round Rock, TX (US);
Joaquin Hinojosa, Round Rock, TX (US);
Ronald N. Kalla, Round Rock, TX (US);
Bruce J. Ronchetti, Austin, TX (US);
Balaram Sinharoy, Poughkeepsie, NY (US);
Eric J. Fluhr, Round Rock, TX (US);
Joaquin Hinojosa, Round Rock, TX (US);
Ronald N. Kalla, Round Rock, TX (US);
Bruce J. Ronchetti, Austin, TX (US);
Balaram Sinharoy, Poughkeepsie, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
In a system with multiple execution units, instructions are queued to allow efficient dispatching. One load/store unit (LSU) may have a store instruction pending to a real address and a second LSU may have a load instruction pending to the same real address. An SMT system has an atomic store quad word (SQW) instruction with a data path that is only double wide and the SQW requires two cycles to complete. The SMT system requires a method to prevent between collisions in a store reorder queue (SRQ) STQ. The real address of a load word (LW) one thread is compared to the real addresses in the SRQ of the second thread. If the SQW with a real address matching the real address of the LW has not committed both of its double words, then the LW of the second thread is rejected.