The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2005

Filed:

Jul. 20, 2001
Applicants:

Steven C. Miller, Livermore, CA (US);

Daniel E. Lenoski, San Jose, CA (US);

Kevin Knecht, Chippewa Falls, WI (US);

George Hopkins, Chippewa Falls, WI (US);

Michael S. Woodacre, Sutton Benger, GB;

Inventors:

Steven C. Miller, Livermore, CA (US);

Daniel E. Lenoski, San Jose, CA (US);

Kevin Knecht, Chippewa Falls, WI (US);

George Hopkins, Chippewa Falls, WI (US);

Michael S. Woodacre, Sutton Benger, GB;

Assignee:

Silicon Graphics, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F012/00 ;
U.S. Cl.
CPC ...
Abstract

A multiprocessor system and method includes a processing sub-system having a plurality of processors and a processor memory system. A scalable network is operable to couple the processing sub-system to an input/output (I/O) sub-system. The I/O sub-system includes a plurality of I/O interfaces. Each I/O interface has a local cache and is operable to couple a peripheral device to the multiprocessor system and to store copies of data from the processor memory system in the local cache for use by the peripheral device. A coherence domain for the multiprocessor system includes the processors and processor memory system of the processing sub-system and the local caches of the I/O sub-system.


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