The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 27, 2005
Filed:
Dec. 30, 2002
Mark Ward, West Linn, OR (US);
David Abercrombie, Gresham, OR (US);
Larry Kelley, Portland, OR (US);
Mark Ward, West Linn, OR (US);
David Abercrombie, Gresham, OR (US);
Larry Kelley, Portland, OR (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A method of increasing the wafer yield for an integrated circuit includes the steps of receiving as input a shot map, an initial orientation of a center of the shot map relative to a center of a wafer resulting in a maximum number of printable die, a usable wafer diameter, a selected yield margin, and historical yield information for each die location in the shot map; generating a plot of an estimated yield for each die location in the wafer from the historical yield information; plotting an estimated wafer yield within an area of the wafer as a function of a radius; and selecting a sweet spot radius corresponding to an area of the wafer having a wafer yield that is substantially equal to the selected yield margin for finding an offset from the initial orientation of the center of the shot map that results in a maximum wafer yield.