The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 27, 2005
Filed:
Nov. 18, 2003
Subramanian Ramesh, Cupertino, CA (US);
Ruggero Castagnetti, Menlo Park, CA (US);
Ramnath Venkatraman, San Jose, CA (US);
Subramanian Ramesh, Cupertino, CA (US);
Ruggero Castagnetti, Menlo Park, CA (US);
Ramnath Venkatraman, San Jose, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
An improved memory cell architecture is provided herein for reducing, or altogether eliminating, chip-level routing congestion in System-on-Chip environments. Though only a few embodiments are provided herein, features common to the described embodiments include: the formation of bitlines in a lower-level metallization layer of the memory array, and the use of word lines and ground supply lines, both formed in inter-level metallization layer(s) of the memory array, for effective shielding of the bitlines against routing signals in the chip-level routing layer.