The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 27, 2005
Filed:
Aug. 10, 2004
Takatoshi Kato, Yokohama, JP;
Takushi Nishiya, Machida, JP;
Hideyuki Yamakawa, Fujisawa, JP;
Takashi Nara, Takasaki, JP;
Nobuaki Nakai, Takasaki, JP;
Hiroshi Ide, Takasaki, JP;
Shintaro Suzumura, Yokohama, JP;
Terumi Takashi, Chigasaki, JP;
Takatoshi Kato, Yokohama, JP;
Takushi Nishiya, Machida, JP;
Hideyuki Yamakawa, Fujisawa, JP;
Takashi Nara, Takasaki, JP;
Nobuaki Nakai, Takasaki, JP;
Hiroshi Ide, Takasaki, JP;
Shintaro Suzumura, Yokohama, JP;
Terumi Takashi, Chigasaki, JP;
Hitachi Video and Information System, Inc., Yokohama, JP;
Hitachi Global Storage Technologies Japan, Ltd., Odawara, JP;
Abstract
In order to generate a sampling clock having a higher accuracy, a synchronous signal generating circuit is provided with a phase error detector, detecting a phase error of a read out signal digitized on the basis of FDTS algorithm, and a VCO, controlling an oscillation frequency on the basis of a phase error detected by the phase error detector, to generate a synchronous signal by the VCO. On the basis of the synchronous signal generated by the synchronous signal generating circuit, an ADC digitizes the read out signal. The digitized read out signal is then converted to binary data by a detection circuit.