The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 27, 2005
Filed:
Sep. 16, 1998
Joel Page, Austin, TX (US);
Edwin DE Angel, Austin, TX (US);
Wai Laing Lee, Austin, TX (US);
Lei Wang, College Station, TX (US);
Hong Helena Zheng, Irvine, CA (US);
Chung-kai Chow, Austin, TX (US);
Joel Page, Austin, TX (US);
Edwin De Angel, Austin, TX (US);
Wai Laing Lee, Austin, TX (US);
Lei Wang, College Station, TX (US);
Hong Helena Zheng, Irvine, CA (US);
Chung-Kai Chow, Austin, TX (US);
Cirrus Logic, Inc., Austin, TX (US);
Abstract
A power on reset circuit, preferably for an integrated circuit, detects application of voltage, starts a phase locked loop one application of voltage is detected but inhibits all clock used for digital logic operations until voltage stability is achieved. If a switched converter is used, the duty cycle of the switched converter is held at unity for a period of time before it is set to that needed to achieve the desired chip operating voltage. Clocks controlling other circuits can be released in stages after the duty cycle of the switched converter is set to its operating voltage level.