The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2005

Filed:

Oct. 27, 2003
Applicant:

Timothy Lance Blankenship, Austin, TX (US);

Inventor:

Timothy Lance Blankenship, Austin, TX (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K019/0175 ;
U.S. Cl.
CPC ...
Abstract

An input level translator circuit is provided. The translator circuit is configured to convert a full-range signal into a low-range signal and a high-range signal. A first pass transistor is configured to restrict the voltage of the full-range signal to provide a high-range voltage at a high-range node when the full-range signal corresponds to a logic 0. A second pass transistor is configured to restrict the voltage of the full-range signal to provide a low-range voltage at a low-range node when the full-range signal corresponds to a logic 1. A first switch circuit is configured to couple the high-range to a first cascode bias signal when the full-range voltage corresponds to a logic 1. A second switch circuit is configured to couple the low-range node to a second cascode bias signal when the full-range voltage corresponds to a logic 0.


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Blankenship, Timothy. (2005). Level translator (U.S. Patent No. 6980032). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6980032

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