The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 20, 2005
Filed:
May. 27, 2003
Franklin L. Duan, San Jose, CA (US);
Subramanian Ramesh, Cupertino, CA (US);
Ruggero Castagnetti, Menlo Park, CA (US);
Franklin L. Duan, San Jose, CA (US);
Subramanian Ramesh, Cupertino, CA (US);
Ruggero Castagnetti, Menlo Park, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A self-aligning memory cell design is provided to allow testing of transistors in every cell of a memory circuit. A test array of these cells is fabricated with contact pads in each cell for specific components in the cell. Then, metal lines are provided to couple the contact pads in the test array. The whole test array is then probed via these metal lines. Tests may then be performed to detect random and systematic transistor degradation electrically for all cells in the circuit. Different components in the memory design may be tested by providing contact pads for the components of interest and providing metal lines coupling the contact pads.