Method and apparatus for reducing power requirements in a multi gigabit parallel to serial converter

Abstract

A variable-mode digital logic circuit is provided for accepting and serializing a parallel data word, so that the parallel data word may be transmitted from the digital logic circuit over a single one-bit wide trace. In some embodiments, the variable-mode digital logic circuit may include a plurality of parallel data traces for receiving the parallel dataword, a plurality of select-capable multiplexor circuits for sequentially activating certain ones of the parallel data traces and for multiplexing the received data into a serial data stream, a ring counter for controlling a frequency of specific operations performed within the circuit, and at least one additional multiplexor circuit array for receiving data output from the plurality of select-capable multiplexor circuits and for further serializing the received data for output on the single one-bit wide trace. The digital logic circuit may be adapted to operate according to one of a plurality of variable modes.