The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 20, 2005
Filed:
Oct. 26, 2001
Sang-ki Kwak, Suwon, KR;
Kwon-young Choi, Seoul, KR;
Young-jae Tak, Suwon, KR;
Myung-jae Park, Kwangju, KR;
Woon-yong Park, Suwon, KR;
Sang-Ki Kwak, Suwon, KR;
Kwon-Young Choi, Seoul, KR;
Young-Jae Tak, Suwon, KR;
Myung-Jae Park, Kwangju, KR;
Woon-Yong Park, Suwon, KR;
Samsung Electronics Co., Ltd., Suwon, KR;
Abstract
An LCD having a plurality of test pads applied with a common voltage, covered with respective shielding conductor or located sufficiently far from pixels. A gate wire including pluralities of gate lines and test pads disconnected from the gate lines and located near one ends of the gate lines, and a common electrode wire including a plurality of common electrodes and a common electrode pad connected to the common electrode electrodes are formed on a substrate, and covered with a gate insulating film. A data wire and a pixel electrode wire are formed thereon and covered with a passivation film. The passivation film and the gate insulating film have contact holes exposing the test pads and the common electrode pad. A plurality of connecting members which are connected to the test pads and the common electrode pad through the contact holes are formed on the passivation film. Alternatively, the passivation film and the gate insulating layer have contact holes exposing only the common electrode pad, and a plurality of shielding members are provided on the passivation layer to be connected to the common electrode pad and to cover the test pads. Alternatively, the distance between the gate lines and the test pads is equal to or larger than twice the width of the pixel.