The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 20, 2005
Filed:
Jan. 20, 2004
Carol Ann Huber, Macungie, PA (US);
Bernard Lee Morris, Emmaus, PA (US);
Makeshwar Kothandaraman, Kamaraka, IN;
Yehuda Smooha, Allentown, PA (US);
Carol Ann Huber, Macungie, PA (US);
Bernard Lee Morris, Emmaus, PA (US);
Makeshwar Kothandaraman, Kamaraka, IN;
Yehuda Smooha, Allentown, PA (US);
Agere Systems Inc., Allentown, PA (US);
Abstract
Using at best a 2.5V nominal power supply, 3.3V technology can be used to implement a 5V tolerant open drain output buffer. High voltage and/or current tolerance is achieved with only the 2.5V power supply. A p-channel FET transistor is connected between a power supply and a node, which in turn is connected to a node between two series output FET transistors. The first transistor is connected between the PAD and node, and the second transistor is connected between the node and ground. The gate of the second transistor is driven from another node formed between a series string of a p-channel FET transistor and an n-channel FET transistor. The other side of the first transistor is connected to the power supply, and the other side of the second transistor is connected to ground. The gates of the transistors of the inverter are tied together and driven by an applied signal.