The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 13, 2005
Filed:
Feb. 22, 2002
Applicants:
Robert Yin, Castro Valley, CA (US);
Mehul R. Vashi, San Jose, CA (US);
Inventors:
Robert Yin, Castro Valley, CA (US);
Mehul R. Vashi, San Jose, CA (US);
Assignee:
Xilinx, Inc., San Jose, CA (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F001/24 ;
U.S. Cl.
CPC ...
Abstract
During a reset condition or prior to system initialization of an FPGA-based system (), a FPGA () can be pre-configured by loading a value from a memory cell () into at least one flip-flop () of the FPGA, which represents a configuration register for an FPGA memory controller (). The FPGA memory controller can be configured using the value loaded in the flip-flop. The value loaded into the flip-flop from the memory cell can be a default value previously stored in the memory cell.