The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 13, 2005
Filed:
Mar. 07, 2002
Chao-peng Chen, Fremont, CA (US);
Kevin Lin, San Ramon, CA (US);
Jei-wei Chang, Cupertino, CA (US);
Kochan Ju, Fremont, CA (US);
Hui-chuan Wang, Pleasanton, CA (US);
Chao-Peng Chen, Fremont, CA (US);
Kevin Lin, San Ramon, CA (US);
Jei-Wei Chang, Cupertino, CA (US);
Kochan Ju, Fremont, CA (US);
Hui-Chuan Wang, Pleasanton, CA (US);
Headway Technologies, Inc., Milpitas, CA (US);
Abstract
A major problem in Lead Overlay design for GMR structures is that the magnetic read track width is wider than the physical read track width. This is due to high interfacial resistance between the leads and the GMR layer which is an unavoidable side effect of prior art methods. The present invention uses electroplating preceded by a wet etch to fabricate the leads. This approach requires only a thin protection layer over the GMR layer to ensure that interface resistance is minimal. Using wet surface cleaning avoids sputtering defects and plating is compatible with this so the cleaned surface is preserved Only a single lithography step is needed to define the track since there is no re-deposition involved.