The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 06, 2005
Filed:
May. 12, 2003
John M. Sharpe, Allentown, PA (US);
Jerome Chu, Allentown, PA (US);
Matthew Moucheron, Allentown, PA (US);
Mary Roby, Plano, TX (US);
John M. Sharpe, Allentown, PA (US);
Jerome Chu, Allentown, PA (US);
Matthew Moucheron, Allentown, PA (US);
Mary Roby, Plano, TX (US);
Agere Systems Inc., Allentown, PA (US);
Abstract
The present invention provides a non-global process for designing an integrated circuit layout. The process comprises locating an isolated layout feature of an integrated circuit layout and non-globally changing at least one lateral dimension of the isolated layout feature to obtain an optimized increment. The change in lateral dimension by the optimized increment does not violate a minimum separation distance between the isolated layout feature and the other adjacent layout features. The process may be incorporated into a system for non-globally modifying an integrated circuit layout, described in a data file or an integrated circuit design system.