The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 06, 2005
Filed:
Sep. 29, 1999
Martin M. Deneroff, Palo Alto, CA (US);
Gregory M. Thorson, Altoona, WI (US);
Randal S. Passint, Chippewa Falls, WI (US);
Martin M. Deneroff, Palo Alto, CA (US);
Gregory M. Thorson, Altoona, WI (US);
Randal S. Passint, Chippewa Falls, WI (US);
Silicon Graphics, Inc., Mountain View, CA (US);
Abstract
A system and method for interconnecting a plurality of processing element nodes within a scalable multiprocessor system is provided. Each processing element node includes at least one processor and memory. A scalable interconnect network includes physical communication links interconnecting the processing element nodes in a cluster. A first set of routers in the scalable interconnect network route messages between the plurality of processing element nodes. One or more metarouters in the scalable interconnect network route messages between the first set of routers so that each one of the routers in a first cluster is connected to all other clusters through one or more metarouters.