Apparatus and method for dual access to a banked and pipelined data cache memory unit

Abstract

In a data cache unit that exchanges data signal groups with at least two execution units, the operation of the data cache unit is implemented as a three-stage pipeline in order to access data at the speed of the system clock. For a READ operation, virtual address components are applied to a storage cell bank unit implemented in SAM technology to begin access of the storage cells with the data signal group identified by the virtual address components. The virtual address components are also applied to a microtag unit, the microtag unit identifying a subgroup of the signal group identified by the address components. Simultaneously, the virtual address is formed from the two virtual address components and applied to a translation table unit, to a valid-bit array unit, and to a tag unit. The translation table unit and the tag unit determine whether the correct data signal subgroup identified by the address signal group is stored in the data cache memory unit. The selected data signal subgroup and a HIT/MISS signal are transmitted to the execution unit during the same cycle. For a WRITE operation, only two pipeline stages are required. In addition, the WRITE operation can involve the storage in the data cache memory of a single data signal group or a plurality of data signal groups. Because the storage cells are arranged in banks, simultaneous interaction by the two execution units is possible.