The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 06, 2005

Filed:

Jun. 30, 2000
Applicants:

Douglas E. Duschatko, McKinney, TX (US);

Lane B. Quibodeaux, Allen, TX (US);

Robert A. Hall, Richardson, TX (US);

Andrew J. Thurston, Allen, TX (US);

Inventors:

Douglas E. Duschatko, McKinney, TX (US);

Lane B. Quibodeaux, Allen, TX (US);

Robert A. Hall, Richardson, TX (US);

Andrew J. Thurston, Allen, TX (US);

Assignee:

Cisco Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04J003/06 ; H04L012/26 ;
U.S. Cl.
CPC ...
Abstract

In a data transmission network, such as SONET, a method and apparatus for the generation of a path Alarm Insertion Signal (AIS) at the output of each of a number of concatenated pointer processors in response to a failure at the input of any one of the pointer processors. Each of the pointer processors has an input, an output and a bidirectional terminal that is coupled to a common node. Each of the pointer processors includes circuitry coupled to the input, the output and the bidirectional terminal that causes a predetermined logic level to be asserted at the bidirectional terminal in response to the appearance of an error signal at its input and that causes an AIS to appear at its output in response to either an error signal at its input or the assertion of the predetermined logic level at its bidirectional terminal.


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