The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 06, 2005

Filed:

Feb. 20, 2003
Applicants:

David A. Norte, Westminster, CO (US);

Woong K. Yoon, Westminster, CO (US);

Thu-duyen Ngoc Tran, Denver, CO (US);

Inventors:

David A. Norte, Westminster, CO (US);

Woong K. Yoon, Westminster, CO (US);

Thu-Duyen Ngoc Tran, Denver, CO (US);

Assignee:

Avaya Technology Group, Basking Ridge, NJ (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K009/00 ;
U.S. Cl.
CPC ...
Abstract

An assembly for mitigating at least one of an electrostatic discharge and electromagnetic interference is provided. The assembly includes (a) first and second spaced apart electrical conductorsandand (b) a mitigation moduleelectrically coupled to the first and second spaced apart electrical conductors to control a magnitude of an electrostatic discharge and/or electromagnetic interference in the first and second electrical conductorsand. One or more of the following statements is true: (i) the mitigation modulecomprises a ferrite material; (ii) the mitigation modulecomprises a lossy dielectric material; and (iii) an equivalent electrical circuit for at least part of the mitigation modulecomprises at least a first circuit segmentcomprising a first inductor and a first capacitor electrically connected in parallel and a second capacitorelectrically connected in series with the first circuit segment. The first and second electrical conductors can be, for example, a ground plane of a printed circuit boardand a wall of the enclosure or chassis


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