The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 06, 2005
Filed:
Dec. 11, 2002
Charles R Keil, Foothill Ranch, CA (US);
Osvaldo Novello, Albazzate, IT;
Roberto Stanich, Milan, IT;
Charles R Keil, Foothill Ranch, CA (US);
Osvaldo Novello, Albazzate, IT;
Roberto Stanich, Milan, IT;
Shipley Company, L.L.C., Marlborough, MA (US);
Abstract
An improved method of and apparatus that is continuously automatically operative in an in-line system is described for applying under vacuum, heat and mechanical pressure a dry film photoresist-forming layer to printed circuit boards () that already have been prelaminated by the loose application thereto of the dry film resist as discrete cut sheets within the confines of the surface of the boards whereby a laminate without entrapped air bubbles and closely conforming to the raised circuit traces and irregular surface contours of the printed circuit board is obtained. Featured is a conveyorized vacuum applicator () comprising two independent vacuum lamination chambers () in end-to-end relation. The first vacuum chamber operates at ambient temperature to draw off all of the air entrapped between the dry film resist and the surface of the printed circuit board at conditions that do not result in premature tacking of the dry film to the surface of the board. Then, in the second vacuum chamber, the photoresist-forming layer is immediately laminated to the printed circuit board under heat and mechanical pressure. The forgoing reduces or eliminates common lamination defects such as premature resist tacking and the attendant need to repair or rework the printed circuit board.