Transfer request pipeline throttling

Abstract

A method and system for a pipelined bus interface macro for use in interconnecting devices within a computer system. The system and method utilizes a pipeline depth signal that indicates a number N of discrete transfer requests that may be sent by a sending device and received by a receiving device prior to acknowledgment of a transfer request by the receiving device. The pipeline depth signal may be dynamically modified, enabling a receiving device to decrement or increment the pipeline depth while one or more unacknowledged requests have been made. The dynamic modifications may occur responsive to many factors, such as an instantaneous reduction in system power consumption, a bus interface performance indicator, a receiving device performance indicator or a system performance indicator.