Method, apparatus and computer program product for high speed memory testing

Abstract

For testing a device under test ('DUT') a test specification is converted in a computer system by a pin vector generator process, which includes generating test vectors. The DUT has numerous input pins and such a pin vector is for a signal to drive one such pin. The pin vectors are compressed and saved. Ones of the pin vectors are loaded, upon initialization of a test, into a pipeline having a series of memory stages and extending from the computer system to channel cards in a test head. The pipeline is operated in data transfer cycles, delivering W bits per cycle. The pin vectors are decompressed at the respective channel cards in decompressor read cycles. X bits are read per decompressor cycle, W being greater than X, so that the pipeline may perform its data transfer cycles less frequently than the decompressor performs its read cycles.