Current limit protection scheme for pwm buck converter with synchronous rectifier

Abstract

A embedded overcurrent protection circuit within the PWM feedback controller () of a power converter () having an novel current limit detection function that minimizes the effects of the turn-on period of the power device () is disclosed herein. This power converter includes a current limit detection circuit () that is reset on the rising edge of the system clock in a first step. In a second step, the power device () that is turned on. In another step, a current detecting circuit () detects the drain-to-source voltage across the power device () and the output current generated thereby. A sense circuit () compares the output current detected with a first predetermined limit value in another step. When the output current is less than the first predetermined limit value, a step is conducted where the output current is regulated by modulating the pulse width of the signal sent by a driver () to the control node of the power device (). In the alternative, when the output current exceeds the first predetermined limit value, the power device () is turned off and the synchronous rectifier () is turned on while its current is monitored at a second predetermined limit value in another step. This synchronous rectifier () monitoring step enables the current limit detection circuit () to minimize the effects of the turn-on period of the power device (). Finally, the current limit detection circuit () is reset on the rising edge of the system clock and wherein this entire procedure is continuous.