Integral nonlinearity error correction for interpolating string dac

Abstract

A segmented string digital-to-analog converter (DAC) comprises least significant bits (LSB subword) interpolation circuitry. The LSB subword interpolation circuitry defines, for each input digital word (or code), an offset voltage representative of an M bit LSB subword of the input digital word. The offset voltage modifies a coarse analog representation voltage of an N bit most significant bits (MSB subword) of the input digital word. The LSB subword interpolation circuitry includes a coarse analog representative voltage input, an LSB subword input, an LSB modification circuit, an offset voltage defining circuit, and a summation device. The DAC further includes a segmented string and a coarse level device connected to tap points of the segmented string. The offset voltage defining circuit receives an LSB subword and defines an offset voltage for modifying the corresponding coarse analog representative voltage. Such an offset voltage is defined based on a given modified LSB subword. The LSB modification circuit modifies the given LSB subword received via the LSB subword input, to create the given modified LSB subword. By modifying the LSB subword, errors introduced due to variations in the upper tap and lower tap voltage levels can be mitigated.