The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 29, 2005

Filed:

Nov. 13, 2001
Applicants:

Akihide Shibata, Nara, JP;

Hiroshi Iwata, Nara, JP;

Seizo Kakimoto, Nara, JP;

Inventors:

Akihide Shibata, Nara, JP;

Hiroshi Iwata, Nara, JP;

Seizo Kakimoto, Nara, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L029/76 ;
U.S. Cl.
CPC ...
Abstract

There is provided a semiconductor device of low power consumption and high reliability having DTMOS' and substrate-bias variable transistors, and portable electronic equipment using the semiconductor device. On a semiconductor substrate (), trilayer well regions () are formed, and DTMOS' () and substrate-bias variable transistors () are provided in the shallow well regions (). Large-width device isolation regions () are provided at boundaries forming PNP, NPN or NPNP structures, where a small-width device isolation region () is provided on condition that well regions on both sides are of an identical conductive type. Thus, a plurality of well regions of individual conductive types where substrate-bias variable transistors () of individual conductive types are provided can be made electrically independent of one another, allowing the power consumption to be reduced. Besides, the latch-up phenomenon can be suppressed.


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