Method of manufacturing a semiconductor device comprising a non-volatile memory with memory cells

Abstract

A method of manufacturing a semiconductor device comprising a non-volatile memory with memory cells (Mij) including a select transistor (T) with a select gate () and including a memory transistor (T) with a floating gate () and a control gate (). In a semiconductor body (), active semiconductor regions are formed which are mutually insulated by field oxide regions (). Next, the surface () is provided with a gate oxide layer () and a first layer of a conductive material wherein the select gate () is etched. Subsequently, the walls of the select gate extending perpendicularly to the surface are provided with an isolating material (). The gate oxide next to the select gate is replaced by a layer of tunnel oxide (). Next, a second layer of a conductive material (), an interlayer dielectric () and a third layer of a conductive material () are deposited. The control gate () extending above and next to the select gate is formed in the third layer. Using the control gate as a mask, the floating gate () is subsequently etched in the second layer of conductive material. In this method, the second layer is deposited in a larger thickness than the select gate, after which this layer is planarized prior to the deposition of the interlayer dielectric and the third layer of conductive material. In this manner, a compact memory cell can be manufactured.