System verifying apparatus and method which compares simulation result based on a random test program and a function simulation

Abstract

An apparatus and method which verify a system including a microprocessor. The apparatus includes first and second simulators which verify a target architecture using a test program and a functional description of the system, respectively. The first and second simlators extract first event information that expresses a verification item relating to a specification of the system. Further, checkers compare results of verification run by the second simulator with results of verification run by the first simulator. The first and second simulators execute an identification of the verification item. The checkers further examine a coverage of the system on the basis of second event information extracted from the verification item with the first event information, if the results of the verification run by the first simulator match the results of the verification run by the second simulator. The second event information is annotation data that describes information on events based on a specification for the system.