The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 22, 2005
Filed:
Dec. 15, 2003
Ta-yung Yang, Milpitas, CA (US);
Cheng-chi Hsueh, Jhong-He, TW;
Ta-yung Yang, Milpitas, CA (US);
Cheng-Chi Hsueh, Jhong-He, TW;
System General Corp., Taipei Hsien, TW;
Abstract
An apparatus for reducing the power consumption of a PFC-PWM power converter is described. The apparatus includes a control terminal used to detect a line-input voltage and to control a PFC signal and a PWM signal. The apparatus further includes a PFC power-manager and a PWM power-manager. The PFC power-manager of the PFC controller determines a PFC-reference voltage for an error amplifier of the PFC controller. The PFC-reference voltage is generated in response to the voltage at the control terminal. The PFC power-manager will disable the PFC signal whenever the voltage at the control terminal drops below a low-voltage threshold voltage. The PWM power-manager will disable the PWM signal whenever the voltage at the control terminal drops below a programmable threshold voltage. Furthermore, the PWM power-manager will pull the voltage at the control terminal low to disable the PFC circuitry during light-load and zero-load conditions.