The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2005

Filed:

Oct. 27, 2003
Applicant:

Weon-ho Park, Suwon, KR;

Inventor:

Weon-Ho Park, Suwon, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L029/00 ;
U.S. Cl.
CPC ...
Abstract

Semiconductor devices and methods for fabricating the same include a device isolation layer formed at a predetermined region of a semiconductor substrate to define a cell active region, a resistor active region, and an MROM active region. The device further includes a floating junction region, a resistive junction region, and a channel junction region, which are formed in the cell active region, the resistor active region, and the MROM active region, respectively. The floating junction region, the resistive junction region, and the channel junction region have the same thickness. A covering gate and an MROM gate cross over the resistive active region and the channel active region, respectively. Also, a memory gate and a select gate cross over the cell active region. The method includes forming a device isolation layer at a predetermined region of a semiconductor substrate to define a cell active region, a resistor active region, and an MROM active region. A floating junction region, a resistive junction region, and a channel junction region are then formed in the cell active region, the resistor active region, and the MROM active region, respectively. Thereafter, a select gate and a memory gate are formed on the cell active region. Also, a covering gate and an MROM gate are formed on the resistor active region and the MROM active region, respectively. The floating junction region, the resistive junction region, and the channel junction region are preferably formed at the same time.


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