The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2005

Filed:

Oct. 29, 2003
Applicants:

Katherine L. Saenger, Ossining, NY (US);

Cyril Cabral, Jr., Ossining, NY (US);

Emanuel I. Cooper, Scarsdale, NY (US);

Hariklia Deligianni, Tenafly, NJ (US);

Panayotis Andricacos, Croton on Hudson, NY (US);

Philippe M. Vereecken, Sleepy Hollow, NY (US);

Inventors:

Katherine L. Saenger, Ossining, NY (US);

Cyril Cabral, Jr., Ossining, NY (US);

Emanuel I. Cooper, Scarsdale, NY (US);

Hariklia Deligianni, Tenafly, NJ (US);

Panayotis Andricacos, Croton on Hudson, NY (US);

Philippe M. Vereecken, Sleepy Hollow, NY (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L021/8283 ;
U.S. Cl.
CPC ...
Abstract

Disclosed is a method for making a metal gate for a FET, wherein the metal gate comprises at least some material deposited by electroplating as well as an FET device comprising a metal gate that is at least partially plated. Further disclosed is a method for making a metal gate for a FET wherein the metal gate comprises at least some plated material and the method comprises the steps of: selecting a substrate having a top surface and a recessed region; conformally depositing a thin conductive seed layer on the substrate; and electroplating a filler gate metal on the seed layer to fill and overfill the recessed region.


Find Patent Forward Citations

Loading…